After physical design is completed, the layout must be fully verified to ensure correct electrical and logical functionality. Some problems found during physical verification can be tolerated if their impact on chip yield is negligible. In other cases, the layout  must be changed, but these changes must be minimal and should not introduce new problems. Therefore, at this stage, layout changes are usually performed manually by experienced design engineers.

• Design rule checking (DRC) verifies that the layout meets all technology imposed constraints. DRC also verifies layer density for chemical-mechanical polishing (CMP).
• Layout vs. schematic (LVS) checking verifies the functionality of the design. From the layout, a netlist is derived and compared with the original netlist produced from logic synthesis or circuit design.
• Parasitic extraction derives electrical parameters of the layout elements from their geometric representations; with the netlist, these are used to verify the electrical characteristics of the circuit.
• Antenna rule checking seeks to prevent antenna effects, which may damage transistor gates during manufacturing plasma-etch steps through accumulation of excess charge on metal wires that are not connected to PN-junction nodes.
• Electrical rule checking (ERC) Verifies the correctness of power and ground connection, and that signal transition times (slew), capacitive loads and fanouts are appropriatelt bounded.

Both analysis and synthesis techniques are integral to the design of VLSI circuits. Analysis typically entails the modeling of circuit parameters and signal transitions, and often involves the solution of various equations using established numerical methods. The choice of algorithms for these tasks is relatively straightforward, compared to the vast possibilities for synthesis and optimization.

Fabrication: The final DRC/LVS/ERC clean layout, usually represented in the GDSII stream format, is sent for manufacturing at a dedicated silicon foundry (fab). The handoff o fthe design to the manufacturing process is called tapeout, even though data transmission from the design team to the silicon fab no longer relies on magnetic tape. Feneration of the data for manufacturing is sometimes referred to as streaming out, reflecting the use of GDSII Stream.

As the fab, the design is patterned onto different layers using photolithographic process. Photomasks are used so that only certain patterns of silicon, specified by the layout, are exposed to a laser light source. Producing an IC requires many masks; modifying the design requires changes to some or all of the masks.

ICs are manufactured on round silicon wafers with diameters ranging from 200mm(8 inches) to 300mm (12 inches). The ICs must then be tested and labeled as either functional and defective, sometimes according to bins depending on the functional or parametric (speed, power) tests that have failed. At the end of the manufacturing process, the ICs are separated, or diced, by sawing the wafer into smaller pieces.

Packaging and Testing: After dicing, fuctional chips are typically packaged. Packaging is configured early in the design process, and reflects the application along with cost and form factor requirements. Package types include DIPs, PGSs, BGAs etc. After a die is positioned in the package cavity, its pins are connected to the package’s pins, eg., with wire bonding  or solder bumps (flip-chip). The package is then sealed.